As transistors are becoming more highly integrated, logic devices trend toward high speed and high integration. With high integration of the transistors, interconnections are increasingly minimized in dimension. Such minimization results in interconnection delay and impediment to high speed operation of the devices.
Rather than aluminum alloy (Al-alloy), copper (Cu) has recently become the interconnection material choice because of its lower resistivity and higher electromigration (EM) resistance properties. However, since it is difficult to etch Cu and since Cu is readily oxidized during an oxidation process, a damascene process is used to form Cu interconnections. According to the damascene process, an interconnection groove where an upper interconnection is to be formed and a via hole connecting the upper interconnection to a lower interconnection or a substrate are formed in an insulating layer. After filling the interconnection groove and the via hole with Cu, chemical mechanical polishing (CMP) is carried out to planarize the above structure. In this manner, the damascene process is a form of filling process.
A low-k dielectric makes it possible to lower the resulting parasitic capacitance between interconnections, enhance device operating speed, and suppress the crosstalk phenomenon. In view of these advantages, the low-k dielectric is being developed in various ways. Generally, the low-k dielectric is classified into a silicon dioxide (SiO2) group organic polymer and a carbon (C) group organic polymer.
A conventional damascene process using a single hard mask layer will now be described with reference to FIG. 1.
Referring to FIG. 1, a lower etch-stop layer 105, a lower insulating layer 110, an upper etch-stop layer 115, an upper insulating layer 120, and a hard mask layer 125 are sequentially stacked on a lower conductive layer 100. The hard mask layer 125, the upper insulating layer 120, the upper etch-stop layer 115, and the lower insulating layer 110 are successively etched to form a via hole 135 exposing the lower etch-stop layer 105. In the drawings, reference symbol “D1” denotes the width of the via hole.
Next, a photoresist pattern 140 with an opening having the width of an interconnection groove is formed. In the drawings, reference symbol “D2” denotes the width of an interconnection. Although not shown in the drawings, an interconnection groove is formed using the photoresist pattern 140 to form a damascene pattern.
In the case where the lower and upper insulating layers 110 and 120 are formed of a low-k dielectric that is an organic polymer, they tend to be damaged by oxygen plasma that is used in an ashing process, for the photoresist pattern 140. In addition, when a rework process is employed wherein a photoresist pattern is removed so as to re-perform the photolithographic process because the initial photolithographic process was incorrect, the insulating layers 110 and 120 that are already exposed at the sidewalls of the via hole can become significantly damaged.
Accordingly in the current dual damascene process that utilizes an insulating layer formed of an organic polymer, a dual hard mask layer is utilized to form an interconnection groove pattern.
FIG. 2A through FIG. 2J show the conventional steps of forming a dual damascene pattern in an insulating layer made of organic polymer using a dual hard mask layer.
Referring to FIG. 2A, a lower etch-stop layer 205, a lower insulating layer 210, an upper etch-stop layer 215, an upper insulating layer 220, a lower hard mask layer 225, and an upper hard mask layer 230 are sequentially stacked on a lower conductive layer 200.
Referring to FIG. 2B, a photoresist pattern 235 with an opening having an interconnection groove width D2 is formed on the upper hard mask layer 230. Using the photoresist pattern 235 as an etching mask, the upper hard mask layer 230 is patterned to form an interconnection groove opening 233 exposing a surface of the lower hard mask layer 225.
Referring to FIG. 2C, the photoresist pattern 235 is removed by an ashing process. The interconnection groove opening 233 is disposed at the upper hard mask layer 230.
Referring to FIG. 2D, a photoresist pattern 240 with an opening having a via hole width is formed on the exposed lower hard mask layer 225. A misalignment may occur in a photolithographic process for forming the photoresist pattern 240, and a photoresist tail 241 may occur after the photolithographic process. The photoresist tail 214 results from a lack of depth of focus (DOF) margin, which is caused by a step difference of the patterned upper hard mask layer 230. The photoresist tail 241 leads to an incorrect pattern, which can prevent formation of a stable damascene structure. In a worst case scenario, a pattern may not be formed.
Referring to FIG. 2E, using the photoresist pattern 240 as an etching mask, the lower hard mask layer 225 is patterned to expose a surface of the upper insulating layer 220.
Referring to FIG. 2F, using the lower hard mask layer 225 as an etching mask, the upper insulating layer 220 is selectively etched to form a hole opening 243 exposing a surface of the upper etch-stop layer 215. Note that the upper insulating layer 220 formed of organic polymer is in the same carbon group as the photoresist pattern 240. Since their etching rates are similar to each other, the photoresist pattern 240 is also removed while etching the upper insulating layer 220.
Referring to FIG. 2G, using the patterned upper hard mask layer 230 as an etching mask, the lower hard mask layer 225 and the exposed upper etch-stop layer 215 are etched to expose an upper side of the upper insulating layer 220 adjacent to the upper portion of the hole opening 243 and the lower insulating layer 210 at a lower portion of the hole opening 243.
Referring to FIG. 2H, the exposed upper insulating layer 220 and the exposed lower insulating layer 210 are patterned to form an interconnection groove 245 in the upper insulating layer as well as a via hole 250 in the lower insulating layer. The interconnection groove 245 is wider than the via hole 250, as shown.
Referring to FIG. 21, the lower etch-stop layer 205 at a lower portion of the via hole 250 is removed to expose a surface of the lower conductive layer 200. At this time, the upper hard mask layer 230 and the exposed etch-stop layer 215 at a lower portion of the interconnection groove 245 may also be removed.
Referring to FIG. 2J, after filling the interconnection groove 245 and the via hole 250 with conductive material, CMP is carried out to form an interconnection 260. Prior to filling the interconnection groove 245 and via hole 250, an optional barrier metal layer 255 may be formed, as shown.
The damascene process using the above dual hard mask layer is relatively complex. Further, as explained above described, this damascene process commonly results in misalignment or the formation of a photoresist tail.